www.azmicrotek.com 1630 s stapley dr, suite 127 +1 - 480- 962- 5881 mesa, az 85204 usa request a sample may 2012, rev 2.1 f eatures ? lvpecl outputs optimized for very low ph ase noise ( - 165dbc/hz) ? greater than 800mhz bandwidth ? fixed 2 output ? 3.0v to 3.6v operation a pplications ? converting crystal or saw based oscillators to lvpecl output p ackage a vailability ? sc70 - 6 o green/rohs compliant/pb - free d escription the azp52 is a sine wave/cmos to lvpecl buffer/divider optimized for very low phase noise ( - 165dbc/hz). it is particularly useful in converting crystal or saw based oscilla tors into lvpecl outputs greater than 800mhz of bandwidth. for greater bandwidth, refer to the azp63 . the azp52 is one of a family of parts that provide options of fixed 1, fixed 2 and selectable 1, 2 modes as well as active high enable or active low enable to osci llator designers. refer to table 2 for the comparison of parts within the azp5x and azp63 family. b lock d iagram az p52 low phase noise sine wave/cmos to lvpecl buffer/divider order number package marking AZP52SG 1 sc 70- 6 c 2 1 tape & reel - add 'r1' at end of order number for 7in (1k parts), 'r2' (2.5k) for 13in 2 see www.azmicrotek.com for date code format www.azmicrotek.com
arizona microtek, inc. az p52 low phase noise sine wave/cmos to lvpecl buffer/divid er www.azmicrotek.com +1 - 480- 962- 5881 2 request a sample may 2012, rev 2.1 p in d escription and c onfiguration table 1 - pin description pin name type function 1 v dd power positive supply 2 gnd power negative supply 3 d input sine or cmos input 4 en input enable 5 q output lvpecl output 6 q output lvpecl output e ngineering n otes f unctionality the azp52 is one of a family of parts that provide options of fixed 1, fixed 2 and selectable 1, 2 modes as well as active high enable or active low enable to oscillator designers. table 2 details the differences between the parts to assist designers in selecting the optimal part for their design. table 3 lists the specific azp52 functional operation. figure 2 plots the s - parameters of the d input. s - parameter and ibis model files for the azp52 are also available for download. table 2 - azp51 - 54 & azp63 family part number divide ratio en logic en pull - up/pull - down bandwidth azp51 1 active high pull - up > 800mhz azp52 2 active high pull - up > 800mhz azp53 selectable 1 or 2 selectable selectable > 800mhz azp54 1 active low pull - down > 800mhz azp63 selectable 1 or 2 selectable selectable 1ghz figure 1 ? pin configuration 1 v dd 3 d 2 gnd 6 q 4 en 5 q c
arizona microtek, inc. az p52 low phase noise sine wave/cmos to lvpecl buffer/divid er www.azmicrotek.com +1 - 480- 962- 5881 3 request a sample may 2012, rev 2.1 table 3 - azp52 functional operation inputs outputs part number en d q ? q azp52 high, nc 1 low low 4 high 4 high high 4 low 4 low x 2 z 3 z 3 1 not connected 2 don't care 3 tri - state 4 every other clock cycle figure 2 - s11 , parameters, d input
arizona microtek, inc. az p52 low phase noise sine wave/cmos to lvpecl buffer/divid er www.azmicrotek.com +1 - 480- 962- 5881 4 request a sample may 2012, rev 2.1 i nput t ermination the d input bias is v dd /2 fed through an internal 10k ? resistor. for clock applications, an input signal of at least 750mv pp ensures the azp52 meets ac specifications. the input should also be ac coupled to maintain a 50% duty cycle on the outputs. the input can be driven to any voltage between 0v and v dd without damage or waveform degradation. d v dd /2 10k? input signal a/r figu re 3 - input termination o utput t ermination t echniques the lvpecl compatible output stage of the azp52 uses a current drive topology to maximize switching speed as illustrated below in figure 4 . two current source pmos transistors (m1 - m2) feed the output pins. m5 is an nmos current source which is switched by m3 and m4. when m4 is on, m5 takes current from m2. this produces an o utput current of 5.1ma (low output state). m3 is off, and the entire 21.1ma flows through the output pin. the associated output voltage swings match lvpecl levels when external 50 ? resistors terminate the outputs. both q and q should always be terminated identically to avoid waveform distortion and circulating current caused by unsymmetrical loads. this rule should be followed even if only one output is in use. v dd (+3.3 v) v bp m1 m2 m3 m4 d v bn m5 21.1ma 21.1ma 16ma v tt = v dd - 2.0v q q 50? 50? 21.1ma - high 5.1ma - low external circuitry output stage figure 4 - typical output termi nation
arizona microtek, inc. az p52 low phase noise sine wave/cmos to lvpecl buffer/divid er www.azmicrotek.com +1 - 480- 962- 5881 5 request a sample may 2012, rev 2.1 d ual s upply lvpecl o utput t ermination the standard lvpecl loads are a pair of 50 ? resistors connected between the outputs and v dd - 2.0v ( figure 4 ). the resistors provide both the dc and the ac loads, assuming 50 ? interconnect. if an additional supply is available within the application, a four resistor termination configuration is poss ible ( figure 5 ). v dd (+3 .3 v) v bp m1 m2 m3 m4 d v bn m5 21.1ma 21.1ma 16ma q q 82? 82? 21.1ma - high 5.1ma - low external circuitry output stage 130? 130? v dd (+3. 3 v) figure 5 - dual supply output termination t hree r esistor t ermination another t ermination variant eliminates the need for the additional supply ( figure 6 ). alternately three resistors and one capacitor accomplish the same termina tion and reduce power consumption. v dd (+3.3 v) v bp m1 m2 m3 m4 d v bn m5 21.1ma 21.1ma 16ma q q 50? 50? 21.1ma - high 5.1ma - low external circuitry output stage 50? 0.01f figure 6 - three resistor termination
arizona microtek, inc. az p52 low phase noise sine wave/cmos to lvpecl buffer/divid er www.azmicrotek.com +1 - 480- 962- 5881 6 request a sample may 2012, rev 2.1 e valuation b oard (ebp53) arizona microtek?s evaluation board ebp53 provides the most convenient way to test and prototype azp52 series circuits. built for the azp53q 1.5x1.0 mm package, it is designed to support both dual and single supply operation. dual supply operation (v dd =+2.0v, v ss = - 1.3v) enables direct coupling to 50 ? time domain test equipment ( figure 7 ). v dd (+2.0 v) v bp m1 m2 m3 m4 d v bn m5 21.1ma 21.1ma 16ma q q 50? 50? 21.1ma - high 5.1ma - low test equipment terminations output stage v ss (-1.3 v) figure 7 - split supply lvpecl output termination ac t ermination clock applications or phase noise/frequency domain testing scenarios typically require ac coupling. figure 8 below shows the ac coupling technique. the 200 ? resistors form the required dc loads, and the 50 ? resistors provide the ac termination. the parallel combination of the 200 ? and 50 ? resistors results in a net 40 ? ac load termination. in many cases this will work well. if necessary, the 50 ? resistors can be increased to about 56 ? . alternately, bias tees combined with current setting resistors will eliminate the lowered ac load impedance. the 50 ? resistors are typically connected to ground but can be connected to the bias level needed by the succeeding sta ge.
arizona microtek, inc. az p52 low phase noise sine wave/cmos to lvpecl buffer/divid er www.azmicrotek.com +1 - 480- 962- 5881 7 request a sample may 2012, rev 2.1 v dd (+3.3 v) v bp m1 m2 m3 m4 d v bn m5 21.1ma 21.1ma 16ma q q 200? 200? 21.1ma - high 5.1ma - low external circuitry output stage 0.01f 0.01f 50? 50? gnd or v t figure 8 - ac termination p erformance data table 4 - absolute maximum ratings absolute maximum ratings are those values beyond which device life may be impaired. symbol characteristic rating unit v dd power supply 0 to +5.5 v v i input voltage - 0.5 to v dd + 0.5 v t a operating temperature range - 40 to +85 c t stg storage temperature range - 65 to +150 c esd hbm human body model 2500 v esd mm machine model 200 v esd cdm charged device model 2500 v
arizona microtek, inc. az p52 low phase noise sine wave/cmos to lvpecl buffer/divid er www.azmicrotek.com +1 - 480- 962- 5881 8 request a sample may 2012, rev 2.1 table 5 - dc characteristics dc characteristics (v dd = 3.0v to 3.6v unless otherwise specified, t a = - 40 to 85 c) symbol characteristic conditions min typ max unit v oh output high voltage 1 - 40 c v dd = 3.3v 2.05 2.415 v 25 c 2.05 2.48 85 c 2.05 2.54 v ol output low voltage 1 - 40 c v dd = 3.3v 1.365 1.615 v 25 c 1.43 1.68 85 c 1.49 1.74 i z output leakage current, tri - state 2 en=low - 10 10 a v ih high level input voltage en 2 v v il low level input voltage en 0.8 v i pd pull - down current en - 2.2 a r bias bias resistor d input to internal v dd /2 reference 10k i dd power supply current 22 35 ma i ddz power supply current d input v il 8 ma outputs tri - state 1 en=low 1 specified with outputs terminated through 50 ? resistors to v dd - 2v or thevenin equivalent. 2 measured at q / q pins. table 6 - ac characteristics ac characteristics (v dd = 3.0v to 3.6v, t a = - 40 to 85 c) symbol characteristic min max unit t r / t f output rise/fall 1,2 80 250 ps (20% - 80%) f max maximum input frequency - sine wave 2 1300 mhz v inmax maximum recommended input signal v dd v p - p v inmin minimum recommended input signal 0.2 v p - p pn phase noise 1,2 - 1mhz offset - 165 dbc/hz 1 specified with outputs terminated through 50 ? resistors to v cc - 2v or thevenin equivalent. 2 1.5 v p - p sine wave input, ac coupled to d pin.
arizona microtek, inc. az p52 low phase noise sine wave/cmos to lvpecl buffer/divid er www.azmicrotek.com +1 - 480- 962- 5881 9 request a sample may 2012, rev 2.1 p ackage d iagram sc70 - 6 green/rohs compliant/pb - free msl=1 arizona microtek, inc. reserves the right to change circuitry and specifications at any time without prior notice. arizona microtek, inc. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does arizona microtek, inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. arizona microtek, inc . does not convey any license rights nor the rights of others. arizona microtek, inc. products are not designed, intended or authorized for use as components in systems intended to support or sustain life, or for any other application in which the failure of the arizona microtek, inc. product could create a situation where personal injury or death may occur. should buyer purchase or use arizona microtek, inc. products for any such unintended or unauthorized application, buyer shall indemnify and hold ariz ona microtek, inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that arizona microtek, inc. was negligent regarding the design or manufacture of the part.
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